AMD Instinct MI400

What the MI400 is

The AMD Instinct MI400 is the next generation of AMD's Instinct family of data-center GPUs for AI work, following the MI350 series. AMD has said the MI400 is expected to land in 2026^[2]. The company has so far presented the chip less as a standalone add-in card than as one component of a rack-level system: its Helios reference design is expected to support both the MI350 series and the MI400 series^[1].

Expected memory and bandwidth

The most concrete public numbers come from ExtremeTech's reporting, which says the MI400 is expected to have 432 GB of HBM4 memory and 19.6 TB/s of memory bandwidth^[2]. HBM, or high-bandwidth memory, is DRAM built up in stacked layers and wired to the processor through a very wide, very short connection, which is how it reaches data rates far beyond ordinary memory chips.

For AI workloads these two numbers do different jobs. Capacity sets how much can be held on the accelerator at once — the weights of a model plus whatever working state the model needs while it runs. Bandwidth sets how fast the compute units can be fed from that memory. A figure such as 19.6 TB/s describes how much data can move between memory and processor every second, and it matters because fast arithmetic hardware is useless if it spends its time waiting for data to arrive.

The Helios rack

AMD previewed its next-generation Helios AI reference design rack, which integrates AMD Instinct MI400 GPUs, EPYC Venice CPUs and Pensando Vulcano NICs^[1]. A reference design of this kind is a complete blueprint for a machine — compute accelerators, host processors and networking — that server makers can build from, rather than a single board.

AMD describes Helios as a unified system built around a tightly coupled scale-up domain of up to 72 MI400 series GPUs, with 260 terabytes per second of scale-up bandwidth and support for Ultra Accelerator Link^[1]. "Scale-up" refers to the group of accelerators connected closely enough to behave like one large machine, the domain in which a single training run or a single large model can be spread across many chips over fast direct links; "scale-out," by contrast, means adding more separate servers across a network. Ultra Accelerator Link, or UALink, is an interconnect standard for exactly that kind of short-reach, high-bandwidth accelerator-to-accelerator traffic.

Because AMD says the rack is expected to support both the MI350 series and the MI400 series^[1], the same system design is meant to carry the current generation of parts and the next one, rather than requiring a new chassis for each GPU generation.

What AMD has not said

AMD has not disclosed MI400 pricing^[2], so the chip's cost relative to the MI350 series is not public. The figures above are expectations attached to a product that AMD has previewed rather than shipped.

Where it sits

The MI400 shows the shape AMD has given its data-center offering: a GPU generation paired with a named rack design, a server CPU generation and a networking chip, so that customers are offered a complete system rather than individual parts^[1]. For readers tracking AI hardware, the entry to watch is the combination — the memory capacity and bandwidth of the accelerator on one side, and the size and bandwidth of the scale-up domain it can join on the other, since the two together set what kind of model can be trained or served on a single rack.