Huawei Ascend 950

What the Ascend 950 series is

The Ascend 950 is a Huawei AI chip family with two members: the Ascend 950PR and the Ascend 950DT. Both are built on the same Ascend 950 die, so the difference between them lies in the memory they are paired with and the workloads they are tuned for, not in the compute core itself^[1]. Huawei announced the series in a keynote by Eric Xu at Huawei Connect on 18 September 2025^[1].

Two chips, two parts of the job

The pair splits the work of running a model. The 950PR is optimized for the prefill stage of inference and for recommendation systems, and was scheduled to be available in the first quarter of 2026 in two forms: a computing card and a SuperPoD server^[1]. The 950DT is optimized for the decode stage of inference and for model training, and was scheduled for the fourth quarter of 2026^[1]. Huawei's roadmap summary carries the same schedule, listing the 950PR for the first quarter of 2026 and the 950DT for the fourth quarter of 2026^[1].

Prefill is the step where a model reads the prompt and builds up its internal state; decode is the step where it produces output one token at a time. The two stages place different demands on hardware, which is why a vendor might tune separate parts for each rather than sell a single chip for all inference.

Throughput and number formats

Huawei said the Ascend 950 chips deliver 1 PFLOPS in FP8, MXFP8 and its proprietary HiF8 format, and 2 PFLOPS in MXFP4^[1]. A roadmap summary lists support for FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4 and HiF4, together with an interconnect bandwidth of 2 TB/s^[2].

The names are number formats. FP32 stores each value in 32 bits, FP8 in 8 bits, and so on; carrying fewer bits per value lets the same hardware complete more operations per second, at the cost of precision. That is why the MXFP4 figure is twice the FP8 figure. Formats such as MXFP8 and MXFP4 are blocked or scaled variants designed to keep accuracy usable at very low bit widths, and HiF8 and HiF4 are Huawei's own entries in that family.

Interconnect and memory

The chips offer 2 TB/s of interconnect bandwidth, which Huawei said is 2.5 times higher than the Ascend 910C^[1]. Huawei paired the 950 die with two of its own high bandwidth memory (HBM) designs: HiBL 1.0 for the 950PR, which it described as lower cost than HBM3E and HBM4E, and HiZQ 2.0 for the 950DT^[1]. The 950DT with HiZQ 2.0 provides 144 GB of memory and 4 TB/s of memory access bandwidth^[1]. Huawei also said that starting with the Ascend 950PR it would use its own HBM rather than bought-in high bandwidth memory^[3].

A change in the programming model

The 950 chips combine SIMD and SIMT in a single design and shrink memory access granularity from 512 bytes to 128 bytes, changes Huawei said make the chips easier to program and better at fragmented access^[1]. SIMD means one instruction applied to a whole vector of data at once; SIMT means many threads each running the same instruction, the style GPU programmers are used to. Memory access granularity is the smallest chunk of data a request moves: a large granularity wastes bandwidth when the data a program needs is scattered, so cutting it from 512 bytes to 128 bytes makes scattered reads cheaper.

Where it sits

Read together, the announcement describes a particular approach: one compute die combined with different self-designed memory stacks for different stages of inference, and a move away from bought-in HBM beginning with the 950PR^[1][3]. The interconnect improvement is stated relative to Huawei's Ascend 910C, which the company says the 950 beats by a factor of 2.5^[1]. The roadmap places the two chips a few quarters apart, with the prefill- and recommendation-oriented part arriving first and the training- and decode-oriented part following at the end of 2026^[1].