Huawei Ascend 910C

A cloud AI chip from the Ascend line

The Ascend 910C is a data-center chip for artificial intelligence workloads, made by Huawei. It belongs to the Ascend 910 series, which Huawei builds on its Da Vinci architecture and positions for cloud AI training and inference ^[2][3]. The company brought the chip to market in the first quarter of 2025, according to a roadmap published at Huawei Connect 2025 ^[1][3].

Where it sits in the line

Huawei launched the Ascend 310 in 2018 and the Ascend 910 in 2019, so the 910C arrives as a continuation of an existing family rather than the start of a new one ^[3]. Being part of the 910 series also fixes its design lineage: the Da Vinci architecture, aimed at cloud training and inference ^[2][3].

In September 2025 Huawei published its first public three-year Ascend roadmap, and the 910C was the chip named in it, alongside plans for the 950, 960 and 970 ^[1][3]. That document is also where the chip's headline specifications were summarised.

What is inside

According to that roadmap summary, the 910C uses a SIMD architecture and delivers 800 TFLOPS in FP16 ^[1]. SIMD stands for single instruction, multiple data: one instruction is applied to a whole set of numbers at the same time instead of one number after another. Neural networks are largely built from dense matrix arithmetic of exactly this regular, repetitive kind, which is why the approach fits AI workloads.

The chip supports the FP32, HF32, FP16, BF16 and INT8 data formats ^[1]. Having several formats available lets the same hardware run at higher precision when accuracy matters and at lower precision when throughput matters more, a common split between training and inference work.

On the memory side, the 910C carries 128 GB of high-bandwidth memory (HBM) with 3.2 TB/s of memory bandwidth, and its interconnect bandwidth is given as 784 GB/s ^[1]. Memory capacity and bandwidth decide how large a model can sit on the chip and how quickly its weights can be fed to the compute units; interconnect bandwidth decides how quickly chips can exchange data with each other.

Deployment through 2025

Eric Xu said at Huawei Connect 2025 that the Ascend 910C became much better known in the industry during 2025, as Huawei scaled up deployment of the Atlas 900 A3 SuperPoD, a system that uses the chip ^[2]. Visibility for the chip therefore came less from a standalone product launch than from the systems built around it.

Xu also described a stretch of engineering work behind that deployment. He said Huawei's AI research and development teams worked from January to the end of April to make sure the inference capabilities of the Ascend 910B and 910C kept up with customer demand after DeepSeek went open source ^[2]. Open-weight models changed what customers wanted to run, and the work was about matching the chips' inference performance to that demand.

A reference point for later chips

The roadmap gives the 910C a second role as a yardstick. Huawei says the Ascend 950's 2 TB/s interconnect bandwidth is 2.5 times higher than that of the Ascend 910C ^[2]. Stating an improvement as a multiple of an existing, shipping part makes the 910C the baseline against which the next generation is described — which is also why its published specifications are useful to keep on record.