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Huawei Ascend 970

Huawei's Ascend 970 is a planned AI chip announced in September 2025 as the last entry on the company's published roadmap, targeted for the fourth quarter of 2028 with roughly double the compute and wider interconnect and memory bandwidth than the Ascend 960.

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Type
AI accelerator
FP8 (TFLOPS)
4000
Release date
Developer
Huawei

What it is

Ascend 970 is an AI chip that Huawei has placed at the end of its published roadmap. The company announced it at Huawei Connect on 18 September 2025, and said it was planned to go to market in the fourth quarter of 2028.[1][3] It is the last chip on that roadmap: the plan Huawei made public stops there, and nothing beyond it has been published.

Compute targets

The roadmap summary gives the chip 4 PFLOPS in FP8 and 8 PFLOPS in FP4.[2] A petaflop is a quadrillion floating-point operations per second. FP8 and FP4 are low-precision number formats, meaning each number is stored in 8 or 4 bits instead of the 16 or 32 bits of older formats; in AI work this reduces how much data has to be moved and stored at every step, which is why chips intended for large models increasingly quote throughput in these formats.

Eric Xu said that some specifications of the Ascend 970 were still being worked out, and that the goal was to double FP4 and FP8 compute relative to the Ascend 960.[1]

Interconnect and memory

Huawei said the interconnect bandwidth of the 970 will double to 4 TB/s.[1][2] The same roadmap summary put memory access bandwidth at 14.4 TB/s, with memory capacity staying at 288 GB.[2] Xu described the memory side more loosely, saying memory access bandwidth would rise by at least 1.5 times over the Ascend 960.[1]

These two kinds of bandwidth measure different things. Interconnect bandwidth is the speed at which chips pass data to each other; when a model is too large for one chip, the work is spread across many, and those chips spend much of their time exchanging data. Memory access bandwidth is the speed at which a chip reads and writes its own memory. Capacity and bandwidth answer different questions: capacity decides whether a model and its working data fit at all, bandwidth decides how quickly they can be fed to the compute units once they do. A chip that keeps capacity flat while raising bandwidth is aimed at workloads that already fit but are limited by how fast data arrives.

How to read the numbers

The figures come in two different shapes. The 14.4 TB/s memory bandwidth, the 4 TB/s interconnect bandwidth and the 4 and 8 PFLOPS compute figures are specific numbers from the roadmap summary and from Huawei's announcement.[1][2] Xu's statement that memory access bandwidth would rise by at least 1.5 times is a floor rather than a fixed value. The two are consistent in direction but not identical in kind, and both describe targets for a product that, at the time of the announcement, was still some years from the market. Huawei said some specifications were still being worked out, so the published numbers are planning goals rather than measured results.[1]

Where it sits

Announcing a chip three years before it is due to be sold is unusual, and it puts the 970 in a particular position: it is less a product description than the far end of a schedule. Naming it as the last chip on the published roadmap fixes the horizon of Huawei's public plan at the fourth quarter of 2028, and gives the 960, the chip it is measured against, a successor to be compared with. What the announcement does not settle is the final specification. The compute, interconnect and memory figures are the ones Huawei has attached to the 970 so far; the chip itself was still under definition when they were published.[1][2]

TechniquesDeep learning

ApplicationsEnterprise

Ecosystem & regionChinaHardware & compute

Version history

6
  1. 2019
    • Aug 23, 2019 Huawei Ascend 910

      Huawei's Ascend 910 is an AI training processor launched in 2019 alongside the MindSpore framework, rated at 256 teraflops FP16 and used to train the PanGu-α language models on clusters of thousands of chips.

  2. 2023
    • 2023 Huawei Ascend 910B

      Huawei's Ascend 910B is a 2023 volume-production AI chip rated at 320 TFLOPS of FP16, with 32 GB of HBM2e memory, 1.6 TB/s of bandwidth and a 310 W envelope on a 7-nanometer domestic process.

  3. 2025
    • 2025 Huawei Ascend 910C

      Huawei's Ascend 910C is a data-center AI chip in the 910 series, built on the Da Vinci architecture. It reached the market in the first quarter of 2025 with 800 TFLOPS of FP16 compute and 128 GB of HBM.

    • Sep 18, 2025 Huawei Ascend 950

      Huawei's Ascend 950 is a two-chip AI series announced in September 2025, pairing a shared die with Huawei's own high bandwidth memory, up to 2 PFLOPS in low precision formats and 2 TB/s interconnect.

    • Sep 18, 2025 Huawei Ascend 960

      The Ascend 960 is a Huawei AI chip on the company's three-year roadmap, slated for the fourth quarter of 2027 with twice the compute, memory and interconnect ports of the Ascend 950 and support for Huawei's HiF4 4-bit format.

    • Sep 18, 2025 Huawei Ascend 970 · This page

      Huawei's Ascend 970 is a planned AI chip announced in September 2025 as the last entry on the company's published roadmap, targeted for the fourth quarter of 2028 with roughly double the compute and wider interconnect and memory bandwidth than the Ascend 960.

20251

  1. ReleaseHuawei publishes three-year Ascend roadmap

    At Huawei Connect 2025 in Shanghai, Huawei published its first three-year Ascend chip roadmap, running to 2028, alongside new Atlas SuperPoD systems and a pledge to open source CANN.

Developed by1

Huawei

Successor of1

Huawei Ascend 960

Notes and sources

  1. Groundbreaking SuperPoD Interconnect: Leading a New Paradigm for AI Infrastructurehttps://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech
  2. 华为昇腾AI芯片及鲲鹏CPU路线图公布https://cinic.org.cn/zgzz/xw/1605368.html
  3. 华为公布昇腾芯片发展时间表https://m.chinanews.com/wap/detail/chs/zw/10484840.shtml

Cite this page: Huawei Ascend 970. TellWorld, https://www.tellworld.net/compute/huawei-ascend-970. Updated 2026-11-08