Huawei publishes three-year Ascend roadmap

Background

Huawei Connect 2025 ran in Shanghai from 18 to 20 September 2025 ^[1][2]. Ascend is the name Huawei uses for its AI chips, and CANN is the compute architecture for neural networks that goes with them ^[1]. Until this conference the company had not set out a public, multi-year timetable for those chips.

What Xu announced

Eric Xu, Huawei's deputy chairman and rotating chairman, used his keynote on 18 September 2025 to publish a three-year Ascend chip roadmap for the first time ^[2][3]. The roadmap covers three series: the Ascend 950 series, which contains two parts, the 950PR and the 950DT; the Ascend 960 series; and the Ascend 970 series ^[1].

The dates attached to them are the first quarter of 2026 for the 950PR, the fourth quarter of 2026 for the 950DT, the fourth quarter of 2027 for the 960 and the fourth quarter of 2028 for the 970 ^[1][3]. Xu described the plan as a one-year release cycle, with compute doubling at each generation ^[1]. Read against the published dates, that means the 950DT, the 960 and the 970 are each scheduled roughly a year after the one before it.

The constraint the roadmap answers

Xu framed the plan around a limit Huawei says it works within: mainland China will lag in semiconductor process nodes for a relatively long time ^[1]. A process node is the manufacturing generation a chip is built on; smaller nodes normally allow more transistors in a given area, and moving to a new one requires the fabs and tools to be available. Xu's point was that sustained computing capacity therefore has to be built on nodes that are practically available ^[1].

Systems as well as chips

At the same event Huawei announced the Atlas 950 SuperPoD with 8,192 chips, the Atlas 960 SuperPoD with 15,488 chips, and the Atlas 950 and Atlas 960 SuperClusters ^[2]. A super node of this kind links a large number of chips tightly enough that they can be used as one system rather than as separate machines; a super cluster extends that arrangement further. The approach shifts part of the question away from how good a single chip is and towards how many chips can be wired together and kept busy.

Huawei also released version 2.0 of the technical specifications for UnifiedBus, its interconnect protocol, and invited partners to build products on it ^[2]. An interconnect protocol governs how the chips inside such a system exchange data; publishing the specification lets other companies design compatible hardware and software around it.

Software and access

On the software side, Huawei said it would go open source and open access with CANN, its Ascend compute architecture for neural networks, by 31 December 2025 ^[1]. For anyone building on the chips, this layer matters as much as the hardware: it is what compilers, libraries and frameworks talk to when they put a model onto an Ascend device.

Why it matters

Three things were put on record at once: a dated schedule of chips through the fourth quarter of 2028, a set of systems that combine thousands of chips, and a commitment to open up the software stack before the first of those chips arrives ^[1][2][3]. Stated together, they describe a strategy built around the process-node constraint Xu named, in which gains come from generations on available nodes and from assembling large numbers of chips into single systems.

What the roadmap also does is make the company's plans checkable. A multi-year timetable with named parts and quarters can be compared against what actually ships, in a way that a single product launch cannot, while the open-sourcing of CANN sets a date by which others can see how the software layer is built.