Cambricon MLU 690

A flagship chip for large-scale training

The MLU 690 is Cambricon's flagship accelerator, and it entered mass production in early 2026^[1]. Cambricon positions it against very large-scale training workloads — jobs in which a single model is spread across many chips and trained over a long period^[1]. That positioning explains the shape of the specification sheet: each number on it describes how much work one device can hold, and how quickly it can exchange data with the rest of a cluster.

What the specifications describe

The chip uses a dual-die package^[1]. Rather than one piece of silicon, two dies sit in the same package and appear to software as a single accelerator. Splitting the logic across two dies lets a package carry more compute than one die can hold, at the cost of a fast and power-hungry link between the halves — which is why packaging, not only circuit design, becomes a central engineering problem at this scale.

Compute is quoted as more than 700 TFLOPS in FP16^[1]. A TFLOPS is one trillion floating-point operations per second; FP16 is a 16-bit floating-point format that trades precision for throughput and is widely used in training. The figure is a peak rate for one precision, not a measurement of what a real training run will reach: actual throughput depends on the model, the batch size, and how well the software keeps the compute units busy.

Memory is 196 GB of HBM3^[1]. High-bandwidth memory (HBM) stacks DRAM dies vertically and connects them to the compute die through a wide interface, which is how it delivers far more bandwidth than ordinary memory chips. Capacity decides how much of a model and its intermediate activations can stay resident on the device instead of being shuttled back and forth to other chips; HBM3 is the generation of the memory standard the chip uses.

Measured interconnect bandwidth exceeds 890 Gbps^[1]. Interconnect is the plumbing between accelerators. At the scale of very large training runs it often decides whether adding more chips keeps adding speed, because the chips have to exchange gradients and other data constantly.

Where it sits

A part like the MLU 690 is best understood as one element of a system rather than a standalone product. Compute rate, memory capacity, memory bandwidth, inter-chip bandwidth and the software stack have to line up; a strong number in one column does not by itself determine how fast a training job finishes. Cambricon's decision to aim the chip at very large-scale training^[1] places it in the part of the market where customers buy clusters rather than single cards, and where the practical question is how predictably a large number of devices work together.

What the published specifications establish is the class the chip is built for: a dual-die package with a large pool of high-bandwidth memory, a peak FP16 rate above 700 TFLOPS, and an interconnect fast enough to feed multi-chip jobs^[1]. Those are the dimensions on which large training accelerators are compared, and on which the MLU 690 is now entering volume production^[1].

^[1]: 21世纪经济报道，《科创板首支万亿股诞生，寒武纪年内涨超75%》