Huawei Ascend 960

What the Ascend 960 is

The Ascend 960 is an AI chip that Huawei has announced but has not yet shipped. Huawei put it on a three-year chip roadmap presented at Huawei Connect on 18 September 2025^[1], and scheduled it to reach the market in the fourth quarter of 2027^[1][3]. What is known about it comes from Huawei's own roadmap materials: the chip's place in the product line, a set of headline numbers and a few architectural choices. No independent measurements exist yet.

Where it sits in the line

Huawei presented the Ascend 960 as the successor to the Ascend 950, and states its improvements relative to that chip: twice the computing power, twice the memory access bandwidth, twice the memory capacity and twice the number of interconnect ports^[1]. The generational step is thus described as a doubling on four axes at once, rather than a gain in raw arithmetic alone.

The company also said it plans one Ascend release per year, with compute roughly doubling each generation^[1]. A roadmap of that kind is a statement about cadence as much as about silicon: it tells customers roughly when to expect the next part and how much more of it there will be.

The numbers Huawei has given

Huawei said the Ascend 960 will reach 2 PFLOPS in FP8 and 4 PFLOPS in FP4^[1][2]. FLOPS counts floating-point operations per second, and a petaflop is a quadrillion of them. FP8 and FP4 are low-precision number formats that store each value in 8 or 4 bits instead of the 16 or 32 bits older formats use; narrower numbers take less memory and are cheaper to move and multiply, which is why chip designers keep adding such formats.

A roadmap summary put the chip's memory at 288 GB of HBM and its memory bandwidth at 9.6 TB/s^[2]. HBM, or high-bandwidth memory, is DRAM stacked in layers and wired to the processor through a wide interface — the standard way of feeding AI accelerators. The same summary gave the Ascend 960 an interconnect bandwidth of 2.2 TB/s^[2], the rate at which the chip can exchange data with other chips, which matters when many of them are wired together into one system.

Formats and architecture

Huawei said the Ascend 960 will support HiF4, its proprietary 4-bit format, which the company described as more precise than other FP4 implementations on the market^[1]. That comparison is Huawei's own claim; how much precision a 4-bit format can preserve, and what it costs in accuracy, is the sort of question independent benchmarks answer rather than launch presentations.

The chip keeps the microarchitecture introduced with the Ascend 950 series — a combination of SIMD, where one instruction applies to a whole vector of values, and SIMT, where many threads run the same instruction on different data — along with the same list of supported data formats^[2]. Keeping both the architecture and the format list means software written for the earlier series should carry over instead of being rewritten.

How to read the announcement

A roadmap entry is a plan, not a product. The dates and figures above are targets Huawei set for itself; a chip scheduled for the fourth quarter of 2027 has years of design, tape-out and manufacturing between the announcement and a shipping part, and specifications can change in that window. What the announcement does establish is the direction Huawei says it is taking: an annual cadence, a doubling of compute each generation, and an emphasis on proprietary low-precision formats and on interconnect — the parts of an AI system that decide how well many chips work together.