Huawei Ascend 910B

What it is

The Ascend 910B is an AI accelerator from Huawei's Ascend family of chips, built for the matrix-heavy arithmetic behind training and serving neural networks. Huawei's Ascend community describes it as a chip that went into volume production in 2023 and pushed FP16 throughput above 320 TFLOPS, up from the earlier Ascend 910^[2].

The number it is usually quoted by is FP16, or half precision: each number is stored in 16 bits rather than the 32 used by ordinary single precision. Narrower numbers take less memory and less bandwidth to move, which is why FP16 became a common default for deep learning.

The numbers on the table

Huawei's comparison table lists 320 TFLOPS of FP16, 640 TOPS of INT8 and 20 TFLOPS of FP64 for the 910B^[1]. The units matter. TFLOPS counts floating-point operations per second, the kind used while weights and activations stay in floating point; TOPS counts integer operations per second, the kind used once a model has been quantised. INT8 is exactly that: weights and activations squeezed into 8-bit integers, a standard way to serve a trained model with less memory traffic. The FP64 figure, at 20 TFLOPS, is far below the FP16 figure, so double-precision work is not the shape of this chip.

Memory, power and process

The table gives 32 GB of HBM2e memory with 1.6 TB/s of bandwidth^[1]. HBM, or high-bandwidth memory, stacks DRAM dies and connects them to the compute die over a very wide interface, which is how a part reaches bandwidth measured in terabytes per second instead of the tens of gigabytes per second of ordinary DRAM. For large models, whose weights have to be streamed from memory at every step, that bandwidth is often the binding constraint rather than the arithmetic units.

The same table gives a 310 W power envelope and a 7-nanometer domestic process^[1]. A power envelope is the budget that the cooling and power delivery of a server have to be designed around. The process description means the chip is fabricated on a 7-nanometer-class domestic manufacturing line.

Interconnect

Huawei's table names HCCS and PCIe 4.0 as the 910B's interconnect^[1]. PCIe 4.0 is the general-purpose serial link that attaches an accelerator to a host processor and its peripherals. HCCS is Huawei's own link for connecting Ascend chips to each other — the path used when many cards are wired into one training job and must exchange gradients or activations. Interconnect bandwidth often decides how well a workload scales beyond a single device.

No FP8

The table also states that the 910B does not support FP8^[1]. FP8 is an 8-bit floating-point format intended to push throughput higher and cut memory traffic further, at some cost in numerical range and precision. Its absence here means a job that would prefer that format has to run in FP16 or INT8 instead.

Where it sits

The same comparison lists the 910C, which packages two dies and reaches 640 TFLOPS of FP16^[1] — roughly double the 910B figure, obtained by putting two pieces of silicon in one package rather than by building a single larger die. Read together, the table places the 910B between the original 910 and the two-die 910C: a 2023 volume-production part with roughly twice the FP16 throughput of the 910 on one side, and a doubled-up package on the other. For anyone planning clusters, the practical picture is a chip whose memory capacity, bandwidth, power draw and interconnect are all specified together, and whose precision support stops at FP16 and INT8.