Google TPU7x (Ironwood)

What TPU7x is

TPU7x, also called Ironwood, is the seventh generation of Google's Tensor Processing Unit, the accelerator family Google designs for machine-learning workloads. Wikipedia's list of TPU generations records Ironwood as introduced in 2025, with 192 GB of high-bandwidth memory (HBM) and 7.37 TB/s of memory bandwidth.^[3] Google Cloud publishes a specification table for the part alongside its documentation, and the numbers below come from that table and from Google's accompanying description.^[1]

Per-chip numbers

The table lists 2,307 teraflops of peak BF16 compute and 4,614 teraflops of peak FP8 compute for each TPU7x chip.^[1] The FP8 figure is exactly twice the BF16 figure, which is the pattern you expect when a format uses half as many bits per number: the hardware can push twice as many values through the same arithmetic per operation. Memory is listed as 192 GiB of HBM per chip, which Google describes as 192 GB with about 7.37 TB/s of bandwidth.^[1] High memory bandwidth matters because matrix multiplication, the core of most neural-network work, keeps re-reading the same weights and activations; the faster those can be fed to the arithmetic units, the less time those units sit idle.

The table lists two TensorCores and four SparseCores per TPU7x chip.^[1] Each matrix multiply unit is 256 by 256 and supports FP8.^[2] Off the chip, the table lists 1,200 GB/s of bidirectional inter-chip interconnect bandwidth and 100 Gbps of data-centre network bandwidth per chip.^[1] The first figure governs how quickly chips inside the same pod can exchange data with each other; the second governs how quickly the pod talks to the wider network.

How it is packaged and programmed

Google says each TPU7x virtual machine contains 4 TPU chips, and that all TPU7x slices use full-host, 4-chip VMs.^[1] The tpu7x-standard-4t machine type has 224 vCPUs, 960 GiB of instance memory, two physical NICs, up to 400 Gbps of network bandwidth and 768 GiB of total TPU HBM — four times the 192 GiB carried on a single chip, which matches the four-chip VM.^[1]

Programmers do not see one chip as one device. Google says the Ironwood programming model exposes two TPU devices per chip, instead of the single logical core used in earlier generations,^[1] so a 4-chip virtual machine presents eight devices to the framework. On the software side, Google says TPU7x can be programmed with JAX and PyTorch, but does not support TensorFlow.^[1] The matrix unit's 256-by-256 shape and FP8 support are the details a kernel author needs when deciding how to tile a computation across those devices.^[2]

Scale

Google Cloud's specification table lists 9,216 chips per TPU7x pod.^[1] A pod is the unit in which the interconnect design pays off: the 1,200 GB/s of bidirectional chip-to-chip bandwidth is what allows thousands of chips to work on one training job rather than thousands of separate small ones.^[1] The two-devices-per-chip programming model and the full-host VMs are the mechanisms by which that machine is carved up and handed to software.

Where it sits

Ironwood is the seventh generation of a line Google has been building for years, and the recurring headline number is memory bandwidth: 7.37 TB/s appears both in Google's own chip description and in Wikipedia's generation list.^[1][3] The other changes visible in the published specifications are the FP8 matrix units, the doubling of logical devices per chip, the two TensorCores and four SparseCores, and a framework story that covers JAX and PyTorch but not TensorFlow.^[1][2] Those are the concrete design choices a reader can check; how they translate into performance on real workloads depends on the workload, and Google's table gives peak figures rather than measured results.