Google TPU v5p

What TPU v5p is

Google TPU v5p is one of the Tensor Processing Unit generations that Wikipedia lists as introduced in 2023 ^[3]. TPU stands for Tensor Processing Unit, Google's custom accelerator family for machine-learning computation. The v5p material describes the chip at two levels: the individual chip and the pod, a group of chips operated together. The published specification table gives concrete numbers for both levels.

Per-chip compute and memory

Google Cloud's specification table lists 459 teraflops of peak BF16 compute and 459 teraflops of peak FP8 compute for each TPU v5p chip ^[1]. Google's documentation also states that TPU v5p supports FP8 ^[2]. The same table gives each chip 95 GiB of HBM (high-bandwidth memory) and 2,765 GB/s of HBM bandwidth ^[1]. Wikipedia's TPU entry lists 95 GB of HBM and 2,765 GB/s of memory bandwidth for v5p ^[3]. The bandwidth figure is the same in both sources; the capacity appears as 95 GiB in the specification table and 95 GB in the Wikipedia entry ^[1][3].

Core counts

The specification table lists two TensorCores and four SparseCores per TPU v5p chip ^[1]. Google's architecture documentation separately says that TPU v5p has four SparseCores per chip and supports FP8 ^[2]. The two sources agree on the four SparseCores; the TensorCore count in the specification table is two per chip ^[1]. These core counts are part of the published chip description, alongside the compute, memory, and interconnect figures.

Pod scale and interconnect

At pod scale, Google Cloud's table lists 8,960 chips per TPU v5p pod ^[1]. Each chip is specified with 1,200 GB/s of bidirectional inter-chip interconnect bandwidth and 50 Gbps of data-centre network bandwidth ^[1]. The inter-chip interconnect links chips within the pod, while the data-centre network bandwidth is the per-chip network interface; the two are expressed in different units. The combination of an 8,960-chip pod and per-chip interconnect figures means the published description covers a system built from thousands of chips connected by a dedicated chip-to-chip fabric and a data-centre network interface ^[1].

Position in the TPU line

TPU v5p belongs to the TPU generations introduced in 2023 ^[3]. Its published specification emphasizes FP8 support, HBM capacity and bandwidth, core counts, and pod-level scale ^[1][2][3]. The concrete numbers are: 459 teraflops of peak BF16 and FP8 compute per chip, 95 GiB of HBM per chip, 2,765 GB/s of HBM bandwidth per chip, and 8,960 chips per pod ^[1]. The architecture documentation confirms FP8 support and four SparseCores per chip ^[2]. Wikipedia's entry places v5p in the 2023 TPU generation list and gives 95 GB HBM and 2,765 GB/s memory bandwidth ^[3]. Taken together, these figures define v5p's published place in the TPU line: a 2023 generation specified at chip level by its compute, memory, and core counts, and at system level by its pod size and interconnect.