Biren BR100

What the BR100 is

The Biren BR100 is a general-purpose graphics processing unit (GPGPU) — a chip built to run parallel numerical work rather than only drawing images. Biren released it on 9 August 2022, together with a cut-down single-die variant called the BR104.^[1]

Where it came from

The chip was taped out in October 2021 and successfully powered on in March 2022.^[1] Tape-out is the point at which a finished design is handed to a foundry to be manufactured; power-on is the first time the returned silicon is switched on and made to execute instructions. The months between the two are normally spent waiting for fabrication and preparing test boards, so the pair of dates marks the passage from design to working hardware.

How it is built

The BR100 packages two identical dies together. The BR104 uses a single die, so most of its compute and input/output figures are half those of the BR100.^[1] Putting two dies in one package is one way to build a very large accelerator: a lithography tool can only expose a limited area in a single shot, so designs that outgrow that area are either stitched together or split across separate pieces of silicon that behave, from the outside, like one chip.

The chip is manufactured on a 7 nm process and integrates 77 billion transistors.^[1] Biren chief executive Zhang Wen said the die size is around 1,000 square millimetres.^[1] Transistor count, process node and die area together describe how much circuitry the designers could fit and how much of it a single package holds — the raw material from which compute throughput is built.

Claimed performance

Biren claimed the BR100 was the first general-purpose GPU from a Chinese company to reach PFLOPS-level single-chip compute.^[1] One petaflop is a thousand trillion floating-point operations per second, a scale that had previously been associated with the flagship accelerators sold by international vendors.

The company also said the chip's peak compute was more than three times that of the flagship products international vendors were selling at the time.^[1] Such figures are vendor statements about peak throughput. Peak numbers describe a theoretical ceiling — roughly, how many arithmetic operations the hardware can issue per clock cycle multiplied by how fast it is clocked — rather than the speed any particular real workload will reach, which depends on memory traffic, data types and how well software maps onto the hardware.

What was announced alongside it

At the same launch, Biren announced one architecture and two chips, with corresponding OAM modules and PCIe cards, one server and a software stack.^[1] OAM, the OCP Accelerator Module, is a mezzanine form factor in which accelerators are mounted directly onto a server board; a PCIe card is the plug-in format most readers will recognise from ordinary add-in cards. Announcing the modules, a server and a software stack at the same time as the silicon indicates that the launch was aimed at deployable systems rather than at a chip on its own: hardware in a rack has to be powered, cooled and programmed, and a compiler and libraries are what let existing code run on a new instruction set.

Where it sits

The BR100 matters chiefly as a marker of how far Chinese-designed general-purpose GPUs had reached by the middle of 2022: a company was claiming single-chip PFLOPS-level compute^[1] and comparing its peak figures with the international flagship parts of the day^[1], and it presented the chip as part of a full line-up of modules, a server and software^[1]. How much of the claimed peak translates into delivered performance on real workloads is a separate question, settled by measurement and by deployment rather than by the launch specification.