AMD Instinct MI100

What the MI100 is

The AMD Instinct MI100 is a GPU accelerator built on AMD's first-generation CDNA architecture. AMD specifies a 7 nm FinFET process and a 1,502 MHz peak engine clock.^[1][2] CDNA is the name AMD gives to a GPU architecture generation, and the MI100 belongs to the first one. A GPU accelerator is designed to carry out many arithmetic operations in parallel; that parallelism is why such a card needs a large memory system, on-chip cache, and a defined power budget.

Compute layout and throughput

The MI100 contains 120 compute units and 7,680 stream processors.^[1] A compute unit is a block that schedules and issues work, and a stream processor is one of the arithmetic lanes inside it. A program's work is divided across these lanes so that many calculations can proceed at once. This organization is the basic reason GPU accelerators can be useful for large numerical workloads.

AMD rates the card at 11.54 TFLOPS peak FP64, 23.1 TFLOPS peak FP32, and 46.1 TFLOPS peak FP32 matrix performance.^[2] It also lists peak FP16 performance at 184.6 TFLOPS and peak BF16 performance at 92.28 TFLOPS.^[1][2] TFLOPS counts trillions of floating-point operations per second, so these figures are peak rates rather than a promise that every program will reach them. FP64, FP32, FP16, and BF16 are formats that use different numbers of bits to represent values; the matrix figure is a separate rating for matrix-shaped arithmetic.

Memory and power

The MI100 carries 32 GB of HBM2 on a 4,096-bit memory interface. AMD gives the memory data rate as up to 2.40 Gbps and the resulting bandwidth as 1.2288 TB/s.^[1] HBM2 is a stacked memory technology; a wide interface lets the GPU move more data per clock than a narrower one. Board power is 300 W in the 32 GB HBM2 PCIe form factor.^[1] Board power covers the whole add-in card rather than only the GPU die, so it shapes the power delivery and cooling requirements. The 300 W rating belongs specifically to that 32 GB HBM2 PCIe version.

AMD also measured a peak theoretical L2 cache slice bandwidth of 3.07 TB/s on the MI100.^[1] L2 cache is an on-chip memory pool that holds data close to the compute units. The word theoretical marks the upper bound from the design, not a measured result from an application.

Where it sits

The MI100 predates the CDNA 2 generation used in the MI200 series.^[1] That places it in AMD's earlier CDNA generation: it uses the first CDNA architecture, while the MI200 series is associated with CDNA 2. The specifications described here—120 compute units, 7,680 stream processors, 32 GB of HBM2, 1.2288 TB/s of memory bandwidth, and 300 W of board power—define the MI100 version covered by these sources.^[1]