Hygon DCU Shengsuan No. 3

What it is

Shengsuan No. 3 is a deep computing processor from Hygon, built on a GPGPU architecture — the general-purpose graphics processor design that most AI accelerators follow, in which many arithmetic units are driven in parallel by software. Unlike a graphics card made for rendering, a chip like this is meant to run the matrix arithmetic behind neural networks and scientific simulation. Hygon calls the family DCU, for deep computing unit, and the third generation went on the market in 2025^[2].

Hygon does not sell the DCU as a standalone part. It is offered together with the company's x86-compatible CPUs as a combined CPU plus DCU platform, so that a system can be configured with both kinds of processor from one vendor^[1][2].

What is on the chip

The processor is manufactured on a 7 nm process and uses chiplet packaging, meaning the silicon is assembled from multiple smaller dies rather than one large monolithic piece^[1]. It provides 1.8 TB/s of HBM bandwidth^[1]. Bandwidth matters as much as raw arithmetic throughput for this class of chip: large models spend much of their time moving weights and activations between memory and compute units, so a faster link to high-bandwidth memory keeps the arithmetic units fed.

The DCU covers FP64, FP32, FP16, TF32, BF16 and INT8 precisions^[1]. Supporting this spread lets one part serve two rather different jobs. The high-precision formats such as FP64 are what traditional scientific and engineering simulation expects, where rounding error can wreck a result; the lower-precision formats such as BF16 and INT8 are the ones used to train and run neural networks, where shorter numbers mean more operations per second and less memory traffic.

The software side

A processor is only useful if programs can be written for it, and the dominant way of programming GPGPU hardware is NVIDIA's CUDA model. Hygon keeps a CUDA-like programming model through its DTK toolchain, which it says lets most existing GPGPU code compile with little modification^[1]. That is a deliberate choice: developers who already have CUDA-style kernels can move them across with limited rewriting instead of starting again from scratch.

Hygon reported operator coverage above 99% for the chip, and says it supports training of trillion-parameter models^[1]. Operator coverage refers to how many of the standard building blocks a deep learning framework relies on — matrix multiplication, convolution, normalization, activation functions and so on — already have an optimized implementation on the hardware. Anything missing has to be written by hand or run elsewhere, so coverage close to the whole set is what makes a chip practical for general model development rather than a few fixed workloads.

Where it sits

The DCU line is not new hardware looking for its first users. By the end of 2025, Hygon's DCUs had been deployed in more than 20 industries and over 300 application scenarios^[3], which places the third generation on top of an existing installed base rather than at the start of one. In its 2025 annual report, Hygon said Shengsuan No. 3 was in market and that development of Shengsuan No. 4 was progressing well^[2].

Read together, the specifications describe a chip aimed at the general-purpose end of AI acceleration: the wide precision support keeps scientific computing in scope, the CUDA-like toolchain lowers the cost of porting existing code, and the CPU plus DCU packaging lets Hygon sell a complete compute platform rather than a single component.