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The chips that train and run AI models: GPUs, TPUs and other accelerators, and which models were trained on them.
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2026
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Jan 29, 2026
Alibaba T-Head Zhenwu 810E
Zhenwu 810E is an AI processor designed by Alibaba's chip team T-Head, listed in January 2026 with 96 GB of high-bandwidth memory, aimed at training, inference and autonomous driving, and already deployed in large clusters on Alibaba Cloud.
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Jan 26, 2026
Microsoft Maia 200
Microsoft's Maia 200 is an inference accelerator introduced on 26 January 2026, built on TSMC's 3-nanometer process with 216 GB of HBM3e memory and more than 10 petaflops at FP4, aimed at serving models such as OpenAI's GPT-5.2.
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Jan 2026
NVIDIA Rubin
NVIDIA Rubin is NVIDIA’s six-chip AI platform and the successor to Blackwell, announced at CES 2026. It targets lower-cost AI token generation, with partner products and cloud instances scheduled for 2026.
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2026
AMD Instinct MI400
The AMD Instinct MI400 is AMD's next-generation data-center GPU for AI, expected in 2026 with 432 GB of HBM4 memory, and designed to be deployed inside AMD's Helios rack-scale system.
2025
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Dec 2, 2025
AWS Trainium3
AWS Trainium3 is AWS's first 3-nanometer AI chip, delivering 2.52 petaflops of FP8 compute per chip and scaling to 144 chips in a Trn3 UltraServer, available through Amazon EC2 from December 2025.[^1][^2]
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Jun 12, 2025
AMD Instinct MI355X
AMD's data-center GPU for AI, introduced in June 2025 on the CDNA 4 architecture, with 288 GB of HBM3E memory and very high low-precision throughput aimed at generative AI inference, positioned against Nvidia's Blackwell generation.
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Jun 12, 2025
AMD Instinct MI350X
AMD Instinct MI350X is a data-center GPU in AMD's MI350 series, built on the CDNA 4 architecture with up to 288 GB of HBM3E memory, up to 8 TB/s of bandwidth and a 1,000 W board power.
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Mar 18, 2025
NVIDIA GB300 NVL72
A rack-scale NVIDIA system announced in March 2025 that links 72 Blackwell Ultra GPUs and 36 Grace CPUs into one unit, rated at 1.5 times the AI performance of GB200 NVL72.
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2025
Huawei CloudMatrix 384
Huawei CloudMatrix384 is a Huawei Cloud service instance built on Atlas 900 A3 SuperPoDs, each linking up to 384 Ascend 910C chips so that they work as one computer.
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2025
Google TPU7x (Ironwood)
TPU7x (Ironwood) is Google's seventh-generation TPU: 192 GB of high-bandwidth memory per chip, FP8 matrix units, 9,216 chips per pod, and a programming model that exposes two devices per chip.
2024
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Dec 5, 2024
AWS Trainium2
AWS Trainium2 is Amazon Web Services' second-generation machine-learning chip, sold through 16-chip EC2 Trn2 instances and 64-chip Trn2 UltraServers, and pitched by AWS as offering better price performance than comparable GPU instances.
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Dec 2024
Google TPU v6e (Trillium)
Google TPU v6e, also called Trillium, is a Google Cloud AI accelerator whose published specifications cover per-chip BF16 and FP8 compute, high-bandwidth HBM, and pod-scale interconnects for large training jobs.
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Oct 10, 2024
AMD Instinct MI325X
A data-center GPU announced by AMD on 10 October 2024, built on third-generation CDNA with 256 GB of HBM3E memory at 6 TB/s and aimed at models with a trillion parameters.
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Mar 18, 2024
NVIDIA GB200 NVL72
NVIDIA's GB200 NVL72 is a liquid-cooled rack that links 72 Blackwell GPUs and 36 Grace CPUs into a single NVLink domain aimed at trillion-parameter AI. Announced at GTC in March 2024, it is the building block of NVIDIA's Blackwell-generation DGX SuperPOD.
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Mar 18, 2024
NVIDIA B200 (Blackwell)
NVIDIA's data-center GPU for the Blackwell generation, announced in March 2024 as the successor to Hopper, built from two joined dies and paired with NVLink and FP4 support for large-scale AI training and inference.
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2024
Kunlunxin P800
The Kunlunxin P800 is a Chinese AI accelerator launched in 2024, the third generation of Kunlunxin's line, built on its own XPU-P architecture and used in large training clusters and in customer deployments.
2023
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Dec 6, 2023
AMD Instinct MI300X
AMD's data-center GPU for generative AI, released in December 2023. Built on the CDNA 3 architecture with a chiplet design, it leads with 192 GB of HBM3 memory, which AMD contrasted with the 80 GB on Nvidia's H100.
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Dec 2023
Google TPU v5p
Google TPU v5p is a 2023 TPU generation with 459 teraflops of peak BF16 and FP8 compute per chip, 95 GiB of HBM, and 8,960 chips per pod.
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Nov 15, 2023
Microsoft Azure Maia 100
Azure Maia 100 is Microsoft's first custom AI chip, announced in November 2023 and built to train and run large language models inside its own Azure data centres rather than being sold.
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Nov 13, 2023
NVIDIA H200 Tensor Core GPU
NVIDIA's H200, announced in November 2023, is a data center GPU that was the first to use HBM3e memory, offering 141 GB at 4.8 TB/s — nearly double the A100's capacity — and roughly double the H100's inference speed on Llama 2 70B.
2022
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Mar 22, 2022
NVIDIA H100
The NVIDIA H100 is the first data-center GPU built on NVIDIA's Hopper architecture, announced in March 2022 with 80 billion transistors, HBM3 memory, FP8 Tensor Cores and a Transformer Engine aimed at large language models.
2020
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May 14, 2020
NVIDIA A100
NVIDIA's A100 is a data-center GPU, the first built on the Ampere architecture. Announced on 14 May 2020, it introduced third-generation Tensor Cores, the TF32 format and Multi-Instance GPU, and became a standard building block for training large language models.
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2020
Google TPU v4
Google's TPU v4 is a machine-learning chip and supercomputer deployed since 2020, built into 4,096-chip pods with optically reconfigurable networking; PaLM and Gemini models were trained on it.
2018
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2018
Google TPU v3
Google's third-generation Tensor Processing Unit, introduced in 2018, with doubled HBM capacity, higher peak throughput, lower power draw and liquid cooling for denser pods.
2017
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May 2017
Google TPU v2
Google TPU v2 is the second-generation Tensor Processing Unit announced in May 2017. It added floating-point support and the bfloat16 format, and scaled to 256-chip pods rated at 11.5 petaFLOPS.
2015
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2015
Google TPU (first generation)
Google's first-generation Tensor Processing Unit is a custom chip built to speed up neural-network inference in its data centers. Deployed in 2015 and revealed in 2016, it showed that dedicated accelerators could beat CPUs and GPUs on cost-performance.
2010
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Nov 9, 2010
NVIDIA GeForce GTX 580
A consumer graphics card NVIDIA released in November 2010 on its Fermi architecture. Two of them, each with 3 GB of memory, later trained AlexNet, the network that won ILSVRC-2012 and which NVIDIA's timeline credits with sparking the era of modern AI.
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Groq LPU (GroqChip)
GroqChip is Groq's AI processor, built for fully deterministic execution with no run-to-run variation. It pairs a 14-nanometer die with 230 MB of on-die SRAM, up to 750 INT8 TOPS and RealScale chip-to-chip links, and ships both as a chip and on the PCIe GroqCard.
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NVIDIA DGX Spark
NVIDIA's DGX Spark is a desktop-sized AI computer built on the GB10 Grace Blackwell Superchip, pairing a 20-core Arm CPU with a Blackwell GPU and up to 128 GB of unified memory for running large models locally.
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AWS Trainium
AWS Trainium is a chip built by Amazon Web Services for deep learning training, sold through EC2 Trn1 instances that AWS says cut training costs by up to 50% compared with comparable instances.
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AWS Inferentia2
AWS Inferentia2 is Amazon Web Services' second-generation chip built for inference, offering 32 GB of high-bandwidth memory, up to 190 TFLOPS in FP16 and up to 12 chips per EC2 Inf2 instance.
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AWS Inferentia
AWS Inferentia is a custom chip designed by AWS for running trained machine-learning models, sold to customers through EC2 Inf1 instances. It aims to make inference cheaper and faster than general-purpose instances.
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Google TPU v5e
Google TPU v5e is a 2023 machine-learning accelerator chip with one TensorCore per chip, 197 TFLOP of bfloat16 peak compute, and 256-chip pods, positioned for both training and serving.
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NVIDIA GH200 Grace Hopper Superchip
The GH200 Grace Hopper Superchip is an NVIDIA module that puts a 72-core Arm CPU and a Hopper GPU in one package joined by NVLink-C2C, pairing fast HBM with up to 480 GB of CPU memory for AI and technical computing.