Compute

Zhenwu 810E is an AI processor designed by Alibaba's chip team T-Head, listed in January 2026 with 96 GB of high-bandwidth memory, aimed at training, inference and autonomous driving, and already deployed in large clusters on Alibaba Cloud.

ChinaDeep learningHardware & compute

Cambricon's flagship MLU 690, in mass production since early 2026, is a dual-die accelerator with 196 GB of HBM3 memory and more than 700 TFLOPS of FP16 compute, aimed at very large-scale training workloads.

ChinaEnterpriseDeep learning

Huawei's Ascend 970 is a planned AI chip announced in September 2025 as the last entry on the company's published roadmap, targeted for the fourth quarter of 2028 with roughly double the compute and wider interconnect and memory bandwidth than the Ascend 960.

ChinaEnterpriseDeep learning

The Ascend 960 is a Huawei AI chip on the company's three-year roadmap, slated for the fourth quarter of 2027 with twice the compute, memory and interconnect ports of the Ascend 950 and support for Huawei's HiF4 4-bit format.

ChinaEnterpriseDeep learning

Huawei's Ascend 950 is a two-chip AI series announced in September 2025, pairing a shared die with Huawei's own high bandwidth memory, up to 2 PFLOPS in low precision formats and 2 TB/s interconnect.

ChinaEnterpriseDeep learning

SK hynix said on 19 March 2025 that it was the first to supply 12-layer HBM4 samples, a stack offering more than 2 TB of data per second and 36 GB of capacity, over 60% faster than HBM3E.

EnterpriseDeep learningHardware & compute

Moore Threads' flagship training-and-inference GPU card, built on the PH100 chip and the Pinghu architecture, rated at 1,000 TFLOPS of dense AI compute with 80 GB of memory, and the company's main shipping product in 2025.

ChinaEnterpriseDeep learning

Hygon's Shengsuan No. 3 is a GPGPU-architecture deep computing processor that reached the market in 2025, built on a 7 nm chiplet design with 1.8 TB/s of HBM bandwidth and a CUDA-like software stack.

ChinaEnterpriseDeep learning

Huawei CloudMatrix384 is a Huawei Cloud service instance built on Atlas 900 A3 SuperPoDs, each linking up to 384 Ascend 910C chips so that they work as one computer.

ChinaEnterpriseDeep learning

Huawei's Ascend 910C is a data-center AI chip in the 910 series, built on the Da Vinci architecture. It reached the market in the first quarter of 2025 with 800 TFLOPS of FP16 compute and 128 GB of HBM.

ChinaEnterpriseDeep learning

TPU7x (Ironwood) is Google's seventh-generation TPU: 192 GB of high-bandwidth memory per chip, FP8 matrix units, 9,216 chips per pod, and a programming model that exposes two devices per chip.

Deep learningReasoningHardware & compute

Google TPU v6e, also called Trillium, is a Google Cloud AI accelerator whose published specifications cover per-chip BF16 and FP8 compute, high-bandwidth HBM, and pod-scale interconnects for large training jobs.

Deep learningHardware & computeData & datasets

SK hynix's 12-layer HBM3E, announced in mass production on 26 September 2024, was the first 12-die high-bandwidth memory stack: 36 GB in a package no thicker than the eight-layer version, running at 9.6 Gbps.

EnterpriseDeep learningHardware & compute

Meta's second-generation in-house AI chip, published on 10 April 2024, built on TSMC's 5-nanometer process and aimed at the ranking and recommendation models Meta runs in its own data centers.

EnterpriseDeep learningHardware & compute

Cerebras's third-generation wafer-scale AI chip, announced in March 2024: 4 trillion transistors on one 46,225-square-millimetre piece of silicon, built to keep very large models in a single memory space.

Large language modelsDeep learningHardware & compute

Intel Gaudi 3 is an AI accelerator introduced in 2024, built from two 5 nm compute dies with 128 GB of HBM2e and 1,835 TFLOPS of BF16 and FP8 matrix throughput, plus integrated 200GbE networking on its OAM module.

EnterpriseDeep learningHardware & compute

The Kunlunxin P800 is a Chinese AI accelerator launched in 2024, the third generation of Kunlunxin's line, built on its own XPU-P architecture and used in large training clusters and in customer deployments.

ChinaDeep learningHardware & compute

Google TPU v5p is a 2023 TPU generation with 459 teraflops of peak BF16 and FP8 compute per chip, 95 GiB of HBM, and 8,960 chips per pod.

Deep learningHardware & computeData & datasets

MTIA v1 is Meta's first-generation in-house AI inference accelerator, built on TSMC's 7 nm process with 128 MB of on-chip memory and designed for deep learning recommendation models.

EnterpriseDeep learningHardware & compute

Huawei's Ascend 910B is a 2023 volume-production AI chip rated at 320 TFLOPS of FP16, with 32 GB of HBM2e memory, 1.6 TB/s of bandwidth and a 310 W envelope on a 7-nanometer domestic process.

ChinaDeep learningHardware & compute

NVIDIA's China-specific data-center GPU, built to stay inside US export controls. Cut down from the H100 in core count and performance, it was still the most advanced NVIDIA chip legally sold in China until April 2025.

ChinaEnterpriseDeep learning

Cambricon's MLU 590 is a 7 nm cloud AI chip released in 2023 for both training and inference on models with hundreds of billions of parameters, and the centrepiece of the company's fifth-generation MLUarch line.

ChinaEnterpriseDeep learning

Biren's general-purpose GPU, released in August 2022, packages two dies on a 7 nm process with 77 billion transistors; the company claimed PFLOPS-level single-chip compute, a first for a Chinese firm.

ChinaEnterpriseDeep learning

NVIDIA's A800 is a data-center GPU that went into production in 2022 as a China-market alternative to the A100, with a reduced chip-to-chip transfer rate to meet US export-control thresholds.

ChinaEnterpriseDeep learning

AMD's data-center GPU accelerator launched on 8 November 2021, built on the CDNA 2 architecture with 220 compute units, 128 GB of HBM2e memory, and strong double-precision throughput alongside low-precision AI formats.

EnterpriseDeep learningHardware & compute

Cambricon's third-generation cloud AI chip, released in 2021: a 7 nm chiplet design with two compute dies, 256 TOPS at INT8, LPDDR5 memory and multi-chip interconnect, positioned for cost-effective inference.

ChinaEnterpriseDeep learning

NVIDIA's third-generation DGX system, unveiled on 14 May 2020: eight A100 GPUs, 320 GB of GPU memory, five petaflops of rated AI performance, and the ability to split into as many as 56 instances.

EnterpriseDeep learningHardware & compute

Huawei's Ascend 910 is an AI training processor launched in 2019 alongside the MindSpore framework, rated at 256 teraflops FP16 and used to train the PanGu-α language models on clusters of thousands of chips.

Large language modelsChinaDeep learning

An AI processor from Cerebras Systems that keeps an entire silicon wafer as one chip, holding more than 1.2 trillion transistors and 400,000 cores; the first of a line that reached WSE-3 in 2024.

Research historyDeep learningHardware & compute

NVIDIA's DGX-2, announced in March 2018, packed 16 Tesla V100 GPUs and a new NVSwitch interconnect into one server that NVIDIA described as the first to reach two petaflops for deep learning.

Deep learningProduct historyHardware & compute

Google's third-generation Tensor Processing Unit, introduced in 2018, with doubled HBM capacity, higher peak throughput, lower power draw and liquid cooling for denser pods.

EnterpriseDeep learningHardware & compute

Google TPU v2 is the second-generation Tensor Processing Unit announced in May 2017. It added floating-point support and the bfloat16 format, and scaled to 256-chip pods rated at 11.5 petaFLOPS.

EnterpriseDeep learningHardware & compute

The NVIDIA Tesla P40 is a data-center GPU accelerator described in a September 2016 NVIDIA datasheet. Built on the Pascal architecture and aimed at deep learning inference, it pairs 24 GB of memory with 47 TOPS of INT8 throughput in a 250 W PCIe card.

Deep learningProduct historyHardware & compute

NVIDIA's DGX-1, unveiled in April 2016, packed eight Tesla P100 GPUs into a single chassis and was billed as the world's first deep learning supercomputer, turning accelerator count into one purchasable machine.

Deep learningProduct historyHardware & compute

The Tesla P100, announced by NVIDIA in April 2016, was the first data-center GPU on the Pascal architecture, and the first to combine stacked HBM2 memory, half-precision math aimed at deep learning and the NVLink interconnect.

Research historyDeep learningHardware & compute

NVIDIA's Tesla K80 is a dual-GPU data-center accelerator announced in November 2014, putting two GK210 chips, 24 GB of memory and up to 8.74 teraflops of single-precision performance on one 300 W board.

Research historyDeep learningHardware & compute

Cerebras's second-generation wafer-scale chip, presented as the largest AI processor ever made: 2.6 trillion transistors, 850,000 cores and 40 GB of on-wafer memory on a single wafer built on a 7-nanometer process.

Deep learningProduct historyHardware & compute

NVIDIA's DGX Spark is a desktop-sized AI computer built on the GB10 Grace Blackwell Superchip, pairing a 20-core Arm CPU with a Blackwell GPU and up to 128 GB of unified memory for running large models locally.

Consumer appsHardware & computeData & datasets

A data-center GPU on NVIDIA's Ampere architecture, aimed at AI inference and mainstream enterprise workloads, with 24 GB of HBM2 memory, a 165 W power ceiling and the ability to split into as many as four MIG instances.

EnterpriseDeep learningHardware & compute

The NVIDIA A10 is a data-center GPU built on the Ampere architecture that combines graphics, video and AI inference in a single-slot PCIe card with 24 GB of memory, aimed at mainstream enterprise servers.

EnterpriseDeep learningHardware & compute

The NVIDIA Tesla T4 is a 70-watt, single-slot GPU built on the Turing architecture and aimed at AI inference, pairing Tensor Cores with dedicated video transcoding engines in a card that slots into ordinary servers.

Deep learningProduct historyHardware & compute

AWS Trainium is a chip built by Amazon Web Services for deep learning training, sold through EC2 Trn1 instances that AWS says cut training costs by up to 50% compared with comparable instances.

EnterpriseDeep learningHardware & compute

AWS Inferentia2 is Amazon Web Services' second-generation chip built for inference, offering 32 GB of high-bandwidth memory, up to 190 TFLOPS in FP16 and up to 12 chips per EC2 Inf2 instance.

EnterpriseDeep learningHardware & compute

AWS Inferentia is a custom chip designed by AWS for running trained machine-learning models, sold to customers through EC2 Inf1 instances. It aims to make inference cheaper and faster than general-purpose instances.

EnterpriseDeep learningHardware & compute

Google TPU v5e is a 2023 machine-learning accelerator chip with one TensorCore per chip, 197 TFLOP of bfloat16 peak compute, and 256-chip pods, positioned for both training and serving.

EnterpriseDeep learningHardware & compute

Intel Gaudi 2 is a data-centre AI accelerator with 96 GB of HBM2e memory, 432 TFLOPS of BF16 compute and 24 tensor processor cores, built to run the matrix arithmetic behind large neural networks.

EnterpriseDeep learningHardware & compute

The AMD Instinct MI100 is a GPU accelerator built on AMD's first-generation CDNA architecture. It pairs 32 GB of HBM2 memory with peak throughput ratings for double-, single-, and half-precision math.

EnterpriseDeep learningHardware & compute

The GH200 Grace Hopper Superchip is an NVIDIA module that puts a 72-core Arm CPU and a Hopper GPU in one package joined by NVLink-C2C, pairing fast HBM with up to 480 GB of CPU memory for AI and technical computing.

EnterpriseDeep learningHardware & compute

The NVIDIA L40S is a data-centre GPU on Nvidia's Ada Lovelace architecture, pairing 48 GB of ECC memory with AI and graphics throughput in a passive, dual-slot PCIe Gen4 card that omits NVLink and MIG.

EnterpriseDeep learningHardware & compute