Enterprise Compute

Google TPU v2 is the second-generation Tensor Processing Unit announced in May 2017. It added floating-point support and the bfloat16 format, and scaled to 256-chip pods rated at 11.5 petaFLOPS.

NVIDIA's GB200 NVL72 is a liquid-cooled rack that links 72 Blackwell GPUs and 36 Grace CPUs into a single NVLink domain aimed at trillion-parameter AI. Announced at GTC in March 2024, it is the building block of NVIDIA's Blackwell-generation DGX SuperPOD.

SK hynix's 12-layer HBM3E, announced in mass production on 26 September 2024, was the first 12-die high-bandwidth memory stack: 36 GB in a package no thicker than the eight-layer version, running at 9.6 Gbps.

Huawei's Ascend 910C is a data-center AI chip in the 910 series, built on the Da Vinci architecture. It reached the market in the first quarter of 2025 with 800 TFLOPS of FP16 compute and 128 GB of HBM.

Huawei CloudMatrix384 is a Huawei Cloud service instance built on Atlas 900 A3 SuperPoDs, each linking up to 384 Ascend 910C chips so that they work as one computer.

A rack-scale NVIDIA system announced in March 2025 that links 72 Blackwell Ultra GPUs and 36 Grace CPUs into one unit, rated at 1.5 times the AI performance of GB200 NVL72.

SK hynix said on 19 March 2025 that it was the first to supply 12-layer HBM4 samples, a stack offering more than 2 TB of data per second and 36 GB of capacity, over 60% faster than HBM3E.

AMD's data-center GPU for AI, introduced in June 2025 on the CDNA 4 architecture, with 288 GB of HBM3E memory and very high low-precision throughput aimed at generative AI inference, positioned against Nvidia's Blackwell generation.

Huawei's Ascend 950 is a two-chip AI series announced in September 2025, pairing a shared die with Huawei's own high bandwidth memory, up to 2 PFLOPS in low precision formats and 2 TB/s interconnect.

Google's third-generation Tensor Processing Unit, introduced in 2018, with doubled HBM capacity, higher peak throughput, lower power draw and liquid cooling for denser pods.

NVIDIA's third-generation DGX system, unveiled on 14 May 2020: eight A100 GPUs, 320 GB of GPU memory, five petaflops of rated AI performance, and the ability to split into as many as 56 instances.

Cambricon's third-generation cloud AI chip, released in 2021: a 7 nm chiplet design with two compute dies, 256 TOPS at INT8, LPDDR5 memory and multi-chip interconnect, positioned for cost-effective inference.

AMD's data-center GPU accelerator launched on 8 November 2021, built on the CDNA 2 architecture with 220 compute units, 128 GB of HBM2e memory, and strong double-precision throughput alongside low-precision AI formats.

NVIDIA's A800 is a data-center GPU that went into production in 2022 as a China-market alternative to the A100, with a reduced chip-to-chip transfer rate to meet US export-control thresholds.

NVIDIA's fourth-generation DGX system, announced in March 2022, packs eight H100 GPUs linked by NVLink plus BlueField-3 networking, and is rated at 32 petaflops of FP8 AI performance for enterprise AI infrastructure.

Biren's general-purpose GPU, released in August 2022, packages two dies on a 7 nm process with 77 billion transistors; the company claimed PFLOPS-level single-chip compute, a first for a Chinese firm.

Cambricon's MLU 590 is a 7 nm cloud AI chip released in 2023 for both training and inference on models with hundreds of billions of parameters, and the centrepiece of the company's fifth-generation MLUarch line.

NVIDIA's China-specific data-center GPU, built to stay inside US export controls. Cut down from the H100 in core count and performance, it was still the most advanced NVIDIA chip legally sold in China until April 2025.

NVIDIA's H200, announced in November 2023, is a data center GPU that was the first to use HBM3e memory, offering 141 GB at 4.8 TB/s — nearly double the A100's capacity — and roughly double the H100's inference speed on Llama 2 70B.

Intel Gaudi 3 is an AI accelerator introduced in 2024, built from two 5 nm compute dies with 128 GB of HBM2e and 1,835 TFLOPS of BF16 and FP8 matrix throughput, plus integrated 200GbE networking on its OAM module.

Meta's second-generation in-house AI chip, published on 10 April 2024, built on TSMC's 5-nanometer process and aimed at the ranking and recommendation models Meta runs in its own data centers.

Hygon's Shengsuan No. 3 is a GPGPU-architecture deep computing processor that reached the market in 2025, built on a 7 nm chiplet design with 1.8 TB/s of HBM bandwidth and a CUDA-like software stack.

Moore Threads' flagship training-and-inference GPU card, built on the PH100 chip and the Pinghu architecture, rated at 1,000 TFLOPS of dense AI compute with 80 GB of memory, and the company's main shipping product in 2025.

AMD Instinct MI350X is a data-center GPU in AMD's MI350 series, built on the CDNA 4 architecture with up to 288 GB of HBM3E memory, up to 8 TB/s of bandwidth and a 1,000 W board power.

Huawei's Ascend 970 is a planned AI chip announced in September 2025 as the last entry on the company's published roadmap, targeted for the fourth quarter of 2028 with roughly double the compute and wider interconnect and memory bandwidth than the Ascend 960.

The Ascend 960 is a Huawei AI chip on the company's three-year roadmap, slated for the fourth quarter of 2027 with twice the compute, memory and interconnect ports of the Ascend 950 and support for Huawei's HiF4 4-bit format.

Cambricon's flagship MLU 690, in mass production since early 2026, is a dual-die accelerator with 196 GB of HBM3 memory and more than 700 TFLOPS of FP16 compute, aimed at very large-scale training workloads.

Microsoft's Maia 200 is an inference accelerator introduced on 26 January 2026, built on TSMC's 3-nanometer process with 216 GB of HBM3e memory and more than 10 petaflops at FP4, aimed at serving models such as OpenAI's GPT-5.2.

AWS Trainium is a chip built by Amazon Web Services for deep learning training, sold through EC2 Trn1 instances that AWS says cut training costs by up to 50% compared with comparable instances.

AWS Inferentia2 is Amazon Web Services' second-generation chip built for inference, offering 32 GB of high-bandwidth memory, up to 190 TFLOPS in FP16 and up to 12 chips per EC2 Inf2 instance.

Google TPU v5e is a 2023 machine-learning accelerator chip with one TensorCore per chip, 197 TFLOP of bfloat16 peak compute, and 256-chip pods, positioned for both training and serving.

The GH200 Grace Hopper Superchip is an NVIDIA module that puts a 72-core Arm CPU and a Hopper GPU in one package joined by NVLink-C2C, pairing fast HBM with up to 480 GB of CPU memory for AI and technical computing.

MTIA v1 is Meta's first-generation in-house AI inference accelerator, built on TSMC's 7 nm process with 128 MB of on-chip memory and designed for deep learning recommendation models.

The NVIDIA L40S is a data-centre GPU on Nvidia's Ada Lovelace architecture, pairing 48 GB of ECC memory with AI and graphics throughput in a passive, dual-slot PCIe Gen4 card that omits NVLink and MIG.

The AMD Instinct MI100 is a GPU accelerator built on AMD's first-generation CDNA architecture. It pairs 32 GB of HBM2 memory with peak throughput ratings for double-, single-, and half-precision math.

Intel Gaudi 2 is a data-centre AI accelerator with 96 GB of HBM2e memory, 432 TFLOPS of BF16 compute and 24 tensor processor cores, built to run the matrix arithmetic behind large neural networks.

AWS Inferentia is a custom chip designed by AWS for running trained machine-learning models, sold to customers through EC2 Inf1 instances. It aims to make inference cheaper and faster than general-purpose instances.

The NVIDIA A10 is a data-center GPU built on the Ampere architecture that combines graphics, video and AI inference in a single-slot PCIe card with 24 GB of memory, aimed at mainstream enterprise servers.

SambaNova SN40L is an AI chip that SambaNova calls a Reconfigurable Dataflow Unit, pairing dataflow-style parallel execution with a three-tier memory system spanning on-chip SRAM, co-packaged HBM and DDR DRAM.

A data-center GPU on NVIDIA's Ampere architecture, aimed at AI inference and mainstream enterprise workloads, with 24 GB of HBM2 memory, a 165 W power ceiling and the ability to split into as many as four MIG instances.